This relates generally to semiconductor integrated circuits, and more particularly to protection circuitry in an electronic system, deployed at interfaces of the system to external devices.
Advances in the electronics industry have provided various types of modern portable, battery-powered electronic systems and devices. Some of these systems, such as smartphones, tablet devices, e-readers and ultra-portable computers (i.e., “subnotebook” computers), have interfaces that may be connected to external accessory devices that provide various peripheral functions. Such accessories include: external storage devices (e.g., solid-state disk storage); input and output devices, such as printers, keyboards, cameras and gaming controllers; power sources; and communications devices or functions, among others. Often, these accessories connect to the system via standard interfaces and connectors, such as those compliant with the Universal Serial Bus (USB) standard, but in some cases connect via proprietary or other interfaces that are specific to a manufacturer or device type. In any case, as user demand for these portable systems and devices and the ability to access content using these devices continues to increase, so does the demand for improved performance, capability and convenience in the connectivity technologies for coupling accessories to portable electronic systems.
Power considerations are important in the interface between a battery-powered system and an accessory. These considerations are complicated for those interfaces, such as USB Type-C interfaces, which can connect to a wide variety of accessories, particularly where some accessories are powered by the system and thus receive power from the system battery, while others can provide power to the system and can thus charge the battery. In these types of interfaces, it is important to protect the circuitry of the system against excessive reverse current from the accessory, and for those devices that are not intended to charge the battery to block reverse current entirely.
FIG. 1 illustrates a conventional power interface subsystem, such as may be implemented at an accessory interface (e.g., USB) of a smartphone or other portable system powered by battery 2. Battery 2 is capable of powering an accessory via a power connection at terminal ACC_PWR, and/or be charged itself from certain power accessories coupled at terminal ACC_PWR. For example, in modern smartphones, battery 2 is typically a lithium-ion battery, which presents a voltage VBAT at terminal BAT that can range from 6 volts (when fully charged) to below 2.5 volts (when approaching full discharge). Conversely, the accessory to which the smartphone is connected may present a voltage VACC_PWR as high as 20 volts at terminal ACC_PWR. In this conventional power interface subsystem, the current path between terminals BAT and ACC_PWR is controlled by high-voltage n-channel power MOSFET transistors 4HV, 8HV, in response to gate voltages GATE_SNS_CTRL and GATE_PASS_CTRL, respectively, from reverse current protection circuit 10 and current sense and limiter circuit 12. As indicated by their symbols in FIG. 1, transistors 4HV, 8HV are constructed as high-voltage transistors, such as lateral double-diffused MOS transistors (DMOS, or LDMOS), considering the potential for high voltages and currents between terminals BAT and ACC_PWR in this application. Pull-up current sources maintain bias currents IPU at the gates of transistors 4HV, 8HV, as shown in FIG. 1; these current sources may also be controlled by gate voltages GATE_SNS_CTRL and GATE_PASS_CTRL to be deselected when their respective transistors 4HV, 8HV are deselected.
Current sense and limiter circuit 12 operates essentially as a comparator, comparing the voltage at terminal BAT with the voltage at node PMID at the drains of transistors 4HV, 8HV, via the source/drain path of n-channel high voltage MOS transistor 6HV when turned on by gate voltage GATE_SNS_CTRL from reverse current protection circuit 10. In operation, current sense and limiter circuit 12 senses the polarity and magnitude of the voltage across transistor 4HV between terminal BAT and node PMID, which reflects the polarity and magnitude of current flow between terminals BAT and ACC_PWR. A replica of this current is provided by current sense and limiter circuit 12 to an analog-to-digital converter (ADC) (not shown) for use in overall system control. In the event of a short circuit at terminal ACC_PWR, current sense and limiter 12 protects the power interface circuitry by de-asserting gate voltage GATE_PASS_CTRL to turn off transistor 8HV.
In contrast, reverse current protection circuit 10 protects against excessive reverse current from an accessory coupled to terminal ACC_PWR and battery 2. As shown in FIG. 1, reverse current protection circuit 10 is constructed as a differential amplifier, with two input legs coupled across terminals ACC_PWR and BAT and output circuitry that applies gate voltage GATE_SNS_CTRL to the gate of transistor 4HV and that issues a status signal FLAG to the appropriate processor in the integrated circuit in response to the comparison of the voltages VBAT and VACC_PWR. In this conventional architecture, reverse current protection circuit 10 operates in either of two modes, which are: a comparator mode in which transistor 4HV is blocked (signal GATE_SNS_CTRL driven fully to ground) if the voltage VACC_PWR exceeds voltage VBAT by more than a reverse voltage limit, and an ideal diode mode in which the forward voltage between battery 2 and the attached accessory is regulated.
FIG. 2 is an electrical schematic of a conventional construction of reverse current protection circuit 10. In the first input leg, voltage VA is developed at a node between resistor R1 and diode 11A from voltage VBAT, while a voltage VB is developed in the second input leg at a node between resistor R1 and diode 11B from the sum of voltage VACC_PWR and a voltage ±VREV from offset voltage source 20. Offset voltage source 20 is typically constructed to conduct a trimmable current from either of the input legs, which is reflected as an offset ±VREV in the voltage across resistor R1. The polarity of voltage VREV depends on a mode signal MODE that indicates whether reverse current protection circuit 10 is in the ideal diode mode or in the comparator mode; the polarity of voltage +VREV shown in FIG. 1 corresponds to the diode mode. Diodes D1, D2 are connected across the two legs to limit the differential voltage ΔV=|VA−VB| to at most a diode drop. P-channel MOS input transistor 13A in the VA input leg has its source receiving voltage VA via diode 11A, and has its gate connected to its drain and to the gate of p-channel MOS input transistor 13B in the VB input leg. Transistor 13B has its source receiving voltage VB via diode 11B. High voltage p-channel MOS transistors 15HVA, 15HVB in the two input legs are similarly configured as transistors 13A, 13B. The combination of input transistors 13A, 13B and high-voltage input transistors 15A, 15B establishes differential currents in the two legs in response to the differential voltage ΔV. In this conventional arrangement, transistors 15HVA, 15HVB are constructed as high-voltage transistors, such as lateral double-diffused MOS transistors (DMOS, or LDMOS), to protect the rest of reverse current protection circuit 10 against a possible extreme voltage (e.g., on the order of 20 volts) at terminal ACC_PWR.
Enable transistors 16HVA, 16HVB in the two input legs are n-channel MOS transistors that receive a control signal ENABLE at their gates, allowing reverse current protection circuit 10 to be selectively enabled by control circuitry elsewhere in the integrated circuit. N-channel MOS transistors 17HVA, 17HVB, which are typically scaled relative to one another to define the range of the output signal, have their source/drain paths connected between the respective input legs and ground, and their gates controlled by voltage reference 21, forming an active load in the differential amplifier. Output voltage VAOUT, at the drain of transistor 17HVB, reflects the differential voltage ΔV, and is applied to an amplifier of n-channel MOS transistor 19HV (biased by current IPU from a regulated voltage VCP), which produces gate voltage GATE_SNS_CTRL at its drain. High-voltage n-channel MOS transistor 22 also receives voltage VAOUT at its gate, and drives logic signal FLAG from its drain voltage via comparator 24.
In the ideal diode operating mode, offset voltage source 20 pulls current from the VA node to cause an offset between voltages VA and VB such that circuit 10 compares voltage VA=VBAT−VREV with the voltage VB=VACC_PWR. In this mode, circuit 10 regulates the forward voltage from terminal BAT to terminal ACC_PWR to ensure the voltage relationship of VACC_PWR≤(VBAT−VREV). If the voltage VACC_PWR rises too high (i.e., above the voltage VBAT−VREV) in this ideal diode mode, then voltage VAOUT will slew to a higher voltage, turning on transistor 19HV, throttling down the gate voltage GATE_SNS_CTRL, and increasing the on-state resistance of power transistor 4HV. Accordingly, reverse current protection circuit 10 regulates gate voltage GATE_SNS_CTRL at the gate of power transistor 4HV to maintain a forward voltage +VREV from terminal BAT to terminal ACC_PWR, blocking reverse current IREV from terminal ACC_PWR toward battery 2. By operating in this ideal diode mode, two low frequency poles exist in the frequency response of reverse current protection circuit 10, with a dominant pole at the gate of power transistor 4HV, a first non-dominant pole caused by the large output capacitance COUT at terminal ACC_PWR, and a second non-dominant pole appearing at the gate of transistor 19HV (i.e., voltage VAOUT). In this conventional architecture, diode-connected high voltage n-channel MOS transistor 18HV is connected at the gate of amplifier transistor 19HV to push that second non-dominant pole to a higher frequency.
In its comparator mode, reverse current protection circuit 10 permits a controlled reverse current IREV to charge battery 2 from the accessory connected at terminal ACC_PWR. In this mode, offset voltage source 20 pulls current from the VB node to cause an offset between voltages VA and VB such that voltage VA=VBAT+VREV is compared with the voltage VB=VACC_PWR. Circuit 10 thus regulates a negative polarity offset voltage VREV at terminal BAT relative to terminal ACC_PWR, allowing voltage VACC_PWR to exceed voltage VBAT by no more than this reverse voltage |VREV|. Reverse current protection circuit 10 controls the magnitude of the corresponding reverse current IREV by effectively sensing the voltage across the series on-state resistances of transistors 4HV and 6HV, and controlling gate voltage GATE_SNS_CTRL of transistor 4HV in response. If the reverse current IREV from terminal ACC_PWR increases, so that the voltage across the series source/drain paths of transistors 4HV and 6HV exceeds reverse voltage VREV, then voltage VAOUT will slew high, turning on transistor 19HV and pulling gate voltage GATE_SNS_CTRL to ground to fully turn off transistor 4HV. As a result, logic signal FLAG is asserted to indicate this condition.